The semiconductor integrated circuit (IC) industry has experienced rapid growth. In the course of IC evolution, functional density (i.e., the number of interconnected devices per chip area) has generally increased while geometry size (i.e., the smallest component (or line) that can be created using a fabrication process) has decreased. This scaling down process generally provides benefits by increasing production efficiency and lowering associated costs. In some IC designs, such scaling-down has also lead to a desire to replace a conventional polysilicon gate electrode with a metal gate electrode to improve device performance.
One process for forming a metal gate structure (e.g., having a metal gate electrode) is referred to as a “gate last” process, where the final gate stack is fabricated last. This reduces the number of subsequent processes, including high temperature processing, that must be performed after formation of the gate structures. There are challenges to implementing such features and processes in conventional fabrication however. As the gate length and spacing between devices decreases, these problems are exacerbated. For example, during chemical mechanical polishing (CMP) processes, controlling gate height and/or preventing dishing effects (for example, over-polishing) of an inter-layer dielectric layer may present difficulties. Also, it has been observed that dishing effects can cause failure of overlay and alignment mark patterns.
Accordingly, what is needed is a method for fabricating an IC device that addresses the above stated issues.